On the morning of August 27, the 2026 Conference on Domestic AI Computing Infrastructure and Ecosystem Collaboration was held in Mangrove Hall at the Shenzhen World Exhibition & Convention Center (Bao’an). Centering on the RISC-V open-source architecture, the building of domestic computing infrastructure, and collaborative innovation across the AI ecosystem, the conference convened industry associations, government and enterprise organizations, research institutes, and leading technology companies — a full cross-section of industry, academia, and research. Together, participants explored the pathways for technological iteration, real-world deployment, and ecosystem co-creation for domestic computing power in the era of AI agents, with the shared goal of helping China’s AI computing power advance from isolated breakthroughs to large-scale commercialization and all-domain enablement.
Opening Remarks: Building Consensus on the Infrastructure, Anchoring the Direction of Collaboration
Shi Xiaoguang, Chairman of the Telecommunications Terminal Industry Association (TAF), and Li Min, First-Class Researcher of the Shenzhen Municipal Government Services and Data Administration Bureau, delivered remarks in succession. Speaking from the perspectives of the terminal device industry and government data enablement, both expressed high expectations for the innovative development of the Greater Bay Area’s domestic computing power industry and the RISC-V open-source ecosystem — building consensus and setting the tone for industry-wide collaboration.
White Paper Release: Consolidating Bay Area Consensus on the RISC-V Industry
A headline outcome of the conference: Fan Congming — Director of the RISC-V Guangdong Provincial Center and Full-time Vice Chairman of the Shenzhen Artificial Intelligence Industry Association — officially released the RISC-V Industry White Paper for the Guangdong-Hong Kong-Macao Greater Bay Area. The white paper systematically maps the region’s industrial landscape across RISC-V chip R&D, instruction-set ecosystem development, technical validation, and application scenarios, and delivers an incisive assessment of industry trends. It provides an authoritative reference for the standardized, coordinated, and large-scale development of the region’s open-source chip industry, pushing Bay Area RISC-V ecosystem building into a new phase of regulated growth.
Keynote Session: From Root Technologies to Urban Scenarios
In the keynote session, five speakers shared insights spanning root technologies, architectural innovation, technology convergence, and product deployment.
Tang Dan, President of the Beijing Institute of Open Source Chip, explained the core value of the RISC-V instruction set in the AI era, arguing that an open-source instruction set is the key to holding the initiative in the intelligent industry’s development.
Guo Yuansheng — Academician of the National Academy of Artificial Intelligence (USA), Fellow of the Royal Society of Medicine (UK), and Executive Vice Chairman of the China Sensors and IoT Industry Alliance — focused on innovation at the intersection of AI and sensing technologies, stressing that real-world scenarios are the core driver of both technological iteration and conceptual innovation.
Su Zhong, a senior technical expert at Alibaba DAMO Academy, analyzed the architectural innovation directions for RISC-V in the era of AI agents, making the case for its enormous potential to upgrade from embedded applications to a general-purpose intelligent computing infrastructure.
The Vice President of Shenzhen Intellifusion Technologies Co., Ltd. addressed urban AI computing applications, explaining the deployment value and future vision of a Token-based computing power system in urban governance.
Xu Qingwei, Head of Ecosystem Marketing at Lanxin Computing, presented the LX500 product, showcasing deployment results in which a RISC-V + AI converged architecture builds a new type of computing infrastructure.
Cai Wanlin, President of the Product Division at Xiamen Sophgo, focused on the demands of large-model applications, exploring in depth the adaptation logic and R&D directions for intelligent hardware chips.
Roundtable: Opportunities and Challenges for Domestic Computing Power
The closing highlight of the conference was moderated by Fu Wei, RISC-V Ambassador at RISC-V International, with Tang Dan, Su Zhong, Luo Yi, Xu Qingwei, and Cai Wanlin engaging in an in-depth discussion on “Opportunities and Challenges for Domestic Computing Power.” The panel noted that the convergence of a rapidly iterating global open-source ecosystem and the large-model wave has created a rare window of opportunity for independent innovation in domestic computing power. At the same time, real bottlenecks remain: incomplete toolchains, the difficulty of quantizing on-device inference, insufficient hardware-software compatibility, and low ecosystem maturity.
Drawing on Bay Area industry practice, the panel observed that the Greater Bay Area holds full-chain advantages — from instruction-set R&D and chip design to terminal applications and urban scenario deployment. Going forward, the region should rely on deep industry-academia-research-application collaboration, use real-world scenarios to feed technological iteration, continuously improve computing energy efficiency ratios, lower deployment costs, and overcome the barriers to large-scale commercialization — to build a self-reliant, open, and interoperable domestic AI computing power ecosystem.
Through a combination of technical debate, deliverables, and industry discussion, the conference clarified the development path for the RISC-V industry and removed barriers between domestic computing power R&D and real-world deployment. Leveraging Shenzhen’s industrial and scenario advantages, the Greater Bay Area will continue to deepen its work in open-source chips and domestic computing power, accelerate independent innovation in core technologies, and lay a solid computing foundation for the high-quality development of China’s AI industry.